The present invention relates to memory systems, and more particularly, to a memory expansion channel for connecting arrays of memory devices to a memory controller.
Interleaved banks of memory cells can increase memory performance when sequential accesses to memory addresses involve different banks of memory. Interleaved banks of memory cells, along with interface circuits, have been integrated on a single die. For example, Rambus Inc. provides technology for an integrated memory device (e.g., Direct RDRAM(trademark)) employing interleaved banks of memory cells, along with a protocol for connecting a number of such memory devices to a single channel, called a Direct Rambus(trademark) Channel. (Direct Rambus(trademark) Channel and Direct RDRAM(trademark) are registered trademarks of Rambus Inc., Mountain View, Calif.)
However, there are limits to the number of Direct RDRAMs that may be supported by a Direct Rambus Channel. Therefore, it is desirable to provide a memory architecture by which a large number of Direct RDRAMs may be connected to a memory controller. Furthermore, it is desirable that the number of Direct RDRAMs supported by a memory controller can be scaled with minimal impact upon the complexity and performance of the memory controller.